Relating Data Characteristics to Transition Activity in High-Level Static CMOS Design

نویسندگان

  • Russell E. Henning
  • Chaitali Chakrabarti
چکیده

Signiicant power reduction can be obtained in the datapath of a CMOS VLSI circuit if data characteristics are carefully exploited. An improved approach that achieves such reduction by using a new model relating important data characteristics to the transition activity in static CMOS circuits is presented. Speciically, relationships between xed-point, two's complement data and 0 ! 1 transition activity in static CMOS circuits are identiied. Models for computing transition activity in terms of a set of statistical parameters are developed, and their performance compared with the Dual Bit Type model. Then, the use of the relationships and models to analyze and signiicantly reduce 0 ! 1 transition activity with little computational eeort is illustrated by several, high-level synthesis examples.

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Activity models for use in low power, high-level synthesis

Characteristics of the data being processed can be used to reduce the power consumption in the data path of a VLSI circuit by exploiting their relationship with transition activity during highlevel synthesis. Important relationships between fixed-point, two’s complement data characteristics and 0→1 transition activity in static CMOS circuits are presented in this paper. Models for computing tra...

متن کامل

Design of a Low Power Magnetic Memory in the Presence of Process Variations

With the advancement in technology and shrinkage of transistor sizes, especially in technologies below 90 nm, one of the biggest problems of the conventional CMOS circuits is the high static power consumption due to increased leakage current. Spintronic devices, like magnetic tunnel junction (MTJ), thanks to their low power consumption, non-volatility, compatibility with CMOS transistors, and t...

متن کامل

Two Phase Clocked Adiabatic Static CMOS Logic and its Logic Family

This paper proposes a two-phase clocked adiabatic static CMOS logic (2PASCL) circuit that utilizes the principles of adiabatic switching and energy recovery. The low-power 2PASCL circuit uses two complementary split-level sinusoidal power supply clocks whose height is equal to Vdd. It can be directly derived from static CMOS circuits. By removing the diode from the charging path, higher output ...

متن کامل

Low-Power Adder Design for Nano-Scale CMOS

A fast low-power 1-bit full adder circuit suitable for nano-scale CMOS implementation is presented. Out of the three modules in a common full-adder circuit, we have replaced one with a new design, and optimized another one, all with the goal to reduce the static power consumption. The design has been simulated and evaluated using the 65 nm PTM models.

متن کامل

Optimized Standard Cell Generation for Static CMOS Technology

Fabrication of an integrated circuit with smaller area, besides reducing the cost of manufacturing, usually causes a reduction in the power dissipation and propagation delay. Using the static CMOS technology to fabricate a circuit that realizes a specific logic function and occupies a minimum space, it must be implemented with continuous diffusion runs. Therefore, at the design stage, an Euleri...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 2000